1. Technical Field
The present invention relates to computer systems in general and in particular to computer systems which include a data bus which may be controlled by plural masters including a main processor and which allocate bus time according to a predefined arbitration scheme.
2. Description of the Prior Art
It is known in computer systems, such as those conforming to IBM Corporation's Micro Channel architecture, to have multiple masters which each can manage data transfers over the system's main data bus. The use of such masters serves to relieve the main processing unit (CPU) from detailed involvement in data transfers between input /output (I/O) devices and main memory and also from I/O device to I/O device. By offloading these duties the CPU is permitted to more fully concentrate its efforts on processing data and setting up transfers that other devices will execute.
In such systems, priorities are established for the respective devices on the data bus to allocate bus time. The CPU is assigned the default or residual priority recognizing that the main work on the bus is desirably allocated to other devices. If a queue develops the devices including the CPU vie for the bus each arbitration cycle and the highest in priority wins. As burst devices may continually assert their high priority, a "fairness" limitation is often used with the burst devices to force them to wait until the existing queue disappears before they may reenter the queue.
This process works well to efficiently allocate bus time unless the duty on the data bus becomes high. In that case, the CPU gets its chance on the bus infrequently, as the priority scheme permits, and then gets "bumped off" after one bus cycle if another device preempts. This situation can "lock out" the CPU to an extent that it can't perform the preparatory setup needed for data transfers or other activity such as memory access that it requires to perform tasks. When this condition is reached the overall system performance deteriorates and, in an extreme case, there may be a system crash. Overcoming the problem of lock out becomes more complicated in systems with memory cache because the main processor may enter a string of cache hits that avoid the need to capture the data bus to accomplish the needed transfer of information.